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SPI (Serial Peripheral Interface)

phatIOs SPI functionality provides ability to transfer data as a master to the SPI bus available on pins marked SCLK, MOSI, MISO.

phatIO uses the SPI bus for internal communication with the SD card, so code must configure the bus correctly before each transfer and devices must ensure they relinquish the bus after use.

There are a number of SPI examples in the Ideas section

(spi_conf <mode> <data direction> <clock divisor>)

Will configure phatIO’s SPI bus according to the arguments:

mode
The SPI clock mode: 0..3
0 = Sample on Rising, Setup on Falling (CPOL=0, CPHA=0)
1 = Setup on Rising, Sample Falling (CPOL=0, CPHA=1)
2 = Sample on Falling, Setup on Rising (CPOL=1, CPHA=0)
3 = Setup on Falling, Sample on Rising (CPOL=1, CPHA=1)
data direction
The data direction MSB|LSB
MSB most significant bit first
LSB least significant bit first
clock divisor
the SPI clock will be 16MHz/2clock divisor
1 = 8MHz
2 = 4MHz
3 = 2MHz
4 = 1MHz
5 = 500KHz
6 = 250KHz
7 = 125KHz

Because the SPI bus is used for Filesystem access, it must be reconfigured before each use.

(spi <byte> ...)

Evaluates each argument as an unsigned byte and sends on the SPI bus, returns the last byte received.

It is assumed that the bus was configured previously and a pin set high/low to enable a slave device.

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